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Flip-flops store data in a computer chip. A flip-flop copies its input D to its output Q on the rising edge of the clock. For that to work reliably, D has to be stable for a short window before the edge (setup time) and after it (hold time).
If D changes too close to the clock edge, the internal state of the flip-flop can take much longer than normal to resolve — this delay is called metastability. That unresolved state can ripple out through the rest of the design and corrupt it.
This interactive demo lets you sweep a data pulse past a clock edge to see it happen. Drag the slider to move the pulse, and watch X2_IN — the internal storage node — and Q.
Interested to know more?