Tiny Tapeout 9 closed with 95% utilisation! It was our best ever run, with 369 designs submitted from 21 countries.

Among the digital projects we had an Atari 2600 (with games), a wide range of CPUs and even some SDR projects.

On the analog side we had PLLs, opamps, ADCs, DACs and time to digital converters.

For all the projects, check the chip’s page.

I printed the datasheet, and it’s hefty! Download it here.

I’m very happy to announce that my paper about Tiny Tapeout has just been published by the IEEE solid state circuits magazine!

Tiny Tapeout aims to make it easier and cheaper than ever to design and manufacture custom Application-Specific Integrated Circuits (ASICs). I originally conceived of the idea in September 2022 as a way to guarantee silicon for my course participants.

If you’re an IEEE member, you can read it here: https://ieeexplore.ieee.org/document/10584359, otherwise you can read the preprint: https://www.techrxiv.org/users/799365/articles/1165896-tiny-tapeout-a-shared-silicon-tapeout-platform-accessible-to-everyone

Tiny Tapeout 6 marked a significant milestone by introducing support for analog and mixed-signal ASIC designs. This innovation opened up a world of possibilities for open-source chip development, building on the project’s success in the digital realm.

Prior to Tiny Tapeout 6, only digital designs were supported. However, the demand for analog and mixed-signal capabilities was evident. In an interview, Carsten Wulff, Principal IC Scientist at Nordic Semiconductor, expressed his enthusiasm for the open-source ASIC movement, noting that a key strength of this approach lies in the mixed-signal domain. FPGAs and microcontrollers excel in digital applications, but mixed-signal designs on ASICs offer unique advantages and capabilities.

We submitted Tiny Tapeout 2 back in December, and last week I received the chips from Efabless.

Most first chip designs fail, but you never hear about it because the big companies keep it a secret. So we thought - why not do the world’s first public silicon bring up?

Thankfully the chips worked, and you can watch the whole stream here.

We’ve since found 1 errata, but luckily not a show stopper.

I’m very happy to have over 140 designs from 30 countries submitted to Tiny Tapeout 4!

Top level statistics:

• Total standard cells 82126
• Maximum cells used was 6813 for project 033
• Maximum utilisation was 87.18% for project 016
• Total wire length was 2607 mm

Thanks to everyone who submitted and all the contributors. Also a huge thanks to Efabless Corporation for sponsoring the project!

Tiny Tapeout 5 is already open and will close in early November 2023.

Using the Tiny User Project tool, people can quickly submit a Tiny Tapeout design to the MPW lottery. The low barrier to entry makes this a great tool to try variations on a design, test faster I/O speeds on an MPW tapeout, or simply compare tapeout processes using a different submission venue.

@Proppy developed the an easy-to-use tool as an extension to the Tiny Tapeout flow.

Proppy’s template repository uses GitHub actions to add a design to the Efabless Caravel User Project. The actions automatically perform the steps requried to harden the design, generate the necessary GDS files, and even generate a convenient GDS viewer. Additionally, the actions output useful reports on cell resource utilization, manufacturability errors, and the precheck results.

I’m happy to announce that Tiny Tapeout 2 was successfully submitted for manufacture in December 2022! 164 designs were included on the tapeout.

Update! Tiny Tapeout 2 chips are back and working!

If you’re unfamiliar, Tiny Tapeout is an educational project that makes it easier and cheaper than ever to get your digital designs manufactured on a real chip! We had a first trial, Tiny Tapeout in September 2022 that was destined for MPW7.