The metrics for measuring integration density used to be metal half-pitch and gate length. For a while they were about the same number. This number became known as the node or process number.

The half-pitch refers to half the minimum center-to-center distance spacing (or pitch) between Metal 1 lines.

By 1990s these numbers became uncoupled, and the 130nm node actually has 70nm gates. By 2000, the node number “had by then absolutely no meaning” (Paolo Gargini. IEEE article by Samuel K. Moore: The node is nonsense.)

It’s still used as a marketing tool, but it doesn’t really mean anything anymore.

The table above shows how the gate length and metal half width measurements have become uncoupled from the node number. The table came from this interesting video about the latest and smallest process sizes.

Finally, this chart shows how even though the 130nm process is quite old, it and larger/older sizes still account for about 50% of all ASICs made by EuroPractice.

Course feedback

I think that starting from zero you will learn enough Verilog to write something that synthesizes and runs and then they you can harden into a design and that would be a pretty rad intro to to Verilog.

Zbychu (digital course)