What does RTL mean in chip design?

RTL (Register Transfer Level) is a design methodology where data processing is split into smaller steps with the results buffered in registers (flip-flops) between them. As data flows between registers it is called register transfer level.

RTL

Q: What is the difference between RTL and HDL?

HDL (Hardware Description Language) can describe all sorts of things, including netlists, test harnesses, and stimuli. RTL refers specifically to the synthesizable subset of HDL that describes real hardware behaviour — not everything written in Verilog or VHDL is RTL.

Q: Why are registers used in the RTL design methodology?

For reasons of speed and debugging it makes sense to split up data processing into smaller steps and buffer the results in registers. This allows each stage to be analysed and verified independently.

Suggest an improvement

November 12, 2020

People often use the terms RTL and HDL interchangably.

I see it in a bit of a different way, influenced by Mead & Conway’s book “Introduction to VLSI systems”. It’s more of a design methodology.

For reasons of speed and debugging, it makes sense to split up the data processing into smaller steps and buffer the results in registers (small memories usually made up of a stack of flip-flops). As the data flows between registers, it’s called register transfer level.

Here’s a quote from page 105 of the pdf of the book:

rtl

For a different viewpoint, this thread in stackexchange tries to answer the question - what is the difference between RTL and HDL.

I made a video about how flip-flops work, and cover a bit about the difference between combinatorial and sequential logic at the beginning.

Verilog and VHDL are both hardware description langauages (HDLs). They can describe all sorts of things, some of which are implementable by logic synthesis (ie synthesizable) and lots of things which are not. They can both describe netlists, ie the wiring together of pre-existing cells, and can also describe test harnesses and stimuli. The subset of these HDLs that is meant to describe real hardware behaviour (other than as netlist) is often referred to as RTL, but not all of this is synthesizable.

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