This package is very small and cheap to produce. It also has benefits due to the lack of bond wires. Bond wires increase parasitic inductance, and can be a problem for high speed designs.

The downside is that they are very tiny!

The last 5 layers of the Skywater PDK define the layers necessary to build the WLCSP package.

Course feedback

It’s a fairly daunting prospect going into something like an ASIC, but I feel confident now that I could pick another project up and go from the start with the Verilog and end up with something that will hopefully work.

Jamie Iles (digital course)