This package is very small and cheap to produce. It also has benefits due to the lack of bond wires. Bond wires increase parasitic inductance, and can be a problem for high speed designs.

The downside is that they are very tiny!

The last 5 layers of the Skywater PDK define the layers necessary to build the WLCSP package.

Course feedback

I wanted to get my hands dirty and I think your course sums up the whole experience from the ground up. You start by understanding how MOFETs work, get hands-on with Verilog and then all the way to the stage where you can be part of the ASIC shuttle.

Ameen Altajer (digital course)