This package is very small and cheap to produce. It also has benefits due to the lack of bond wires. Bond wires increase parasitic inductance, and can be a problem for high speed designs.

The downside is that they are very tiny!

The last 5 layers of the Skywater PDK define the layers necessary to build the WLCSP package.

Course feedback

Excellent resource for chip design enthusiasts to learn the basics of analog chip design with open source tools.

Kwadwo Opong-Mensah (analog course)