This package is very small and cheap to produce. It also has benefits due to the lack of bond wires. Bond wires increase parasitic inductance, and can be a problem for high speed designs.

The downside is that they are very tiny!

The last 5 layers of the Skywater PDK define the layers necessary to build the WLCSP package.

Course feedback

Zero To Asic is the best chip design course I have ever seen or heard about. Changed my future career goals thanks to this experience.

Kolos (analog course)