This package is very small and cheap to produce. It also has benefits due to the lack of bond wires. Bond wires increase parasitic inductance, and can be a problem for high speed designs.

The downside is that they are very tiny!

The last 5 layers of the Skywater PDK define the layers necessary to build the WLCSP package.

Course feedback

It was a great fun way to introduce people to Verilog and basic digital design in general. You don't have to have done tons of FPGA stuff or be an expert at Verilog at all. If you’re interested in hardware in general I'd say it's accessible.

Matthew Beech (digital course)