This package is very small and cheap to produce. It also has benefits due to the lack of bond wires. Bond wires increase parasitic inductance, and can be a problem for high speed designs.

The downside is that they are very tiny!

The last 5 layers of the Skywater PDK define the layers necessary to build the WLCSP package.

Course feedback

The Zero to Asic analog course is a wonderful course put together by Matt . He and his team have meticulously planned the course with lots of good examples and support to get started with the tools for designing your own chips. Hats off to the team for developing such a course and making it available for the users.

Sudhansu Mishra (analog course)