In this insightful interview, I talk with Carsten Wulff, Principal IC Scientist at Nordic Semiconductor, about all things analog ASIC design.

Carsten kicks things off by sharing a fascinating anecdote about how he ended up designing an analog SAR during his winter holiday in the Norwegian mountains, sparked by the opportunity to include analog designs on Tiny Tapeout 6.

The conversation then shifts to Carsten’s thoughts on the accessibility of 130nm technology for analog design, which he believes is “the last comfortable node”. While larger designs with millions of digital gates might not be suitable, 130nm shines for analog applications, offering a sweet spot between performance and cost-effectiveness.

Hi and happy new year! Welcome to my year in review post of 2023. We’ll revisit the biggest moments of open source semiconductors, the goals I failed and those I met, and set some new ones for 2024!

So, let’s start with the biggest news of 2023.

Last year saw the end of the Google sponsored lottery shuttles. We were expecting around another 8 shuttles for sky130, GF180 and the start of sky90. The last shuttle was GFMPW1, which closed late last year and the Sky 130 PDK is now in the safe hands of the chips alliance.

My VGA clock design is the world’s first certified open source hardware down to the chip level.

Unfortunately the MPW1 chips were very hard to use and the new ones have a different pinout and footprint. I’ve been using the clock design as a test project for all the Tiny Tapeout chips past TT03.

To test the new mux structure introduced at TT04, we ran an experimental TT3.5 chip. The chips are back and the clock works as expected (phew!)

The EU and US have pledged $100B investment in semiconductors with their chips acts. A huge percentage will go to building new fabs, but both acts acknowledge that factories are no use without trained people to run them.

The NSF commissioned a report on research, education and workforce development - recently delivered by Matthew Guthaus, Christopher Batten, Erik Brunvand, Pierre-Emmanuel Gaillardon, David Harris, Rajit Manohar, Pinaki Mazumder, Larry Pileggi & James Stine.

For the last few years I’ve worn an old 4 inch wafer to conferences or whenever I’m teaching in person. People rarely get to handle a wafer and are always interested to know more.

While it’s a fantastic conversation starter, the problem with this necklace is that it’s too hip-hop, and not enough “15 million dollar Nikon Lithography Stepper”. To resolve this annoyance, I decided to make the most ridiculous ASIC bling possible - using my own chips of course! The only thing I kept from the old design was the quick release wafer.

We submitted Tiny Tapeout 2 back in December, and last week I received the chips from Efabless.

Most first chip designs fail, but you never hear about it because the big companies keep it a secret. So we thought - why not do the world’s first public silicon bring up?

Thankfully the chips worked, and you can watch the whole stream here.

We’ve since found 1 errata, but luckily not a show stopper.

I’m very happy to have over 140 designs from 30 countries submitted to Tiny Tapeout 4!

Top level statistics:

• Total standard cells 82126
• Maximum cells used was 6813 for project 033
• Maximum utilisation was 87.18% for project 016
• Total wire length was 2607 mm

Thanks to everyone who submitted and all the contributors. Also a huge thanks to Efabless Corporation for sponsoring the project!

Tiny Tapeout 5 is already open and will close in early November 2023.

The Free Silicon Conference returned to Paris in 2023. There were plenty of great talks and I really enjoyed the conference. I was able to interview the organiser and several speakers:

• Luca Alloatti - organiser
• Thomas Benz - PULP
• Jørgen Kragh Jakobsen - his work on open source silicon in Denmark
• Thomas Parry - startup founder of Spherical Systems
• Rene Scholz - Open source PDK from IHP Microsystems
• Dan Fritchman - Analog tools
• Harald Pretl - Mixed signal design

You can find all the recorded talks here.

I got a once in a lifetime chance to use a particle accelerator to look inside my first ASIC!

It was amazing to be able to see all the different layers and match them up with the design files I sent to Efabless.

So join me on my journey to the Swiss Light Source at the Paul Scherrer Institut where I learnt how they use their synchrotron to make some awesome images!

I also have a public photo album if you want some SLS themed wallpaper!

I had the chance to interview Eric Schlaepfer about his MOnSter 6502, a 6502 processor made out of discrete transistors. For me, one of the most interesting things about this project are the similarities to ASIC design, for example Eric wrote his own LVS tool.

You can find out lots more at his website.