Short articles about my experience with the Google/Efabless/Skywater130 ASIC process, interviews and any other related topics I think are interesting.
After 6 months, 90 participants and 14 designs submitted to MPW2, I’m making the Zero to ASIC course even better! One of the things that’s great about the course is that you can proceed at your own pace. I originally set the course length at 6 weeks, but a lot of people want more time than this. To resolve this I have: removed the expiry date on the discord support, removed the expiry date on office hours.
Livestream with Thomas Parry: analogue design with the open source ASIC tools
There continues to be a lot of interest about analogue design with the open source PDK. To cover this interest, I’ve previously interviewed: Diego about his opamp, Lakshmi about her PLL and Thomas about his satellite transceiver. One of the big changes in MPW2 was the provision of more analogue support in the form of Caravan - a new harness. This is exciting because one of the key advantages of an ASIC over an FPGA is the mixed signal capability.
We did it! 14 people from the course got their designs into the group submission, and the project was accepted for fabrication. Silicon here we come! You can get all the details on all the projects submitted to MPW2 here - you’ll need to select the MPW2 filter. And see how I put the application together here, with the repo here. Project listing RGB Mixer Author: Matt Venn Github: https://github.com/mattvenn/wrapped_rgb_mixer/tree/caravel-mpw-two-c Description: reads 3 encoders and generates PWM signals to drive an RGB LED Frequency counter Author: Matt Venn Github: https://github.
Caravel Wishbone Demo
Caravel is the name of the harness provided by Efabless to make it easier to submit a design to the foundry. Among other things, it provides: The padring 3kB of memory A small RISCV processor called PicoRV32 GPIOs A logic analyser A Wishbone bus For the full details, check the documentation The simplest way to interface between your project and the PicoRV32 is probably the logic analyser. This gives you 128 ins and outs that you can use to configure or debug your design.
MPW2 announced by Efabless
Efabless have announced MPW2! The closing date is the 18th of June. The biggest changes are: OpenLANE ASIC flow updated to rc0.15 Caravel has become caravel_user_project at the mpw-two-c tag: smaller repo size includes a ‘Caravel Lite’ submodule new IRQ ports logic analyser registers renamed An alternative analogue specific ‘Caravan’ harness The submission process has been streamlined to make it faster and easier to submit You can browse the current applications here: https://platform.
Interview With Dan Rodrigues - first shuttle, racing the beam & retro gaming
In this interview Dan and I talk about his submission to the first shuttle, simulating video projects, how to do graphics with no frame buffer and the joys of retro gaming. Caravel repo: https://github.com/dan-rodrigues/caravel_vdp_lite IceStation32: https://github.com/dan-rodrigues/icestation-32
OpenLANE Output Files
OpenLANE makes a lot of output files! This can be quite confusing when you’re getting started. Here’s a useful spreadsheet I made to show: the path of the files most important files and what they mean which tool creates which file Thanks Amr and Ahmed for helping me with this! The spreadsheet was updated for MPW2, and there haven’t been major changes in MPW3. OpenLANE summary tool I’ve also made a summary tool: https://github.
Interview With Thomas Parry - Amateur satellite radio, Open Source vs Industry tools and beautiful analogue layout
In this interview Thomas talks us through his Amateur satellite transceiver shuttle submission. We also discuss the differences between the Open Source tools and the industry standard ones he uses in his day job. Design repo: https://github.com/yrrapt/amsat_txrx_ic Caravel repo: https://github.com/yrrapt/caravel_amsat_txrx_ic Connect with Thomas on linkedin: https://www.linkedin.com/in/thomas-parry-60419468/
My Zero to ASIC journey
Almost exactly a year ago in March 2020 I started getting interested in Open Source ASIC tooling. I don’t remember exactly what sparked my interest, but I remember this talk by Tim Edwards at WOSH: Bootstrapping a real working design flow and sometime after seeing Adam Zeloof posting a picture of an ASIC implementation of pong. I began by investigating QFlow. The standard cells used by QFlow were from Oklahoma State University (OSU).