ASICs pack in billions of transistors per square centimeter, making their construction and functionality impossible to understand with the naked eye.

In fact, the upcoming 2 nanometer technology will be so small* that the transistor dimensions will only be 20X larger than an individual atom.

Wouldn’t it be great to see how ASICs are built in 3D at a scale that our bulky human hands can appreciate?

Well wait no longer! Thanks to Thorsten Knoll’s guide, you can now 3D print the cells that make up an ASIC using the GDS files.

In this interview with Professor James Stine, we talk about:

• Why is Open Source the key to innovation?
• What do students struggle with most when learning to design standard cell libraries?
• What are the biggest misconceptions engineers have about standard cells?
• What’s James’ tool flow?
• How many cells are needed to make a library?
• Why do we need another library for Global Foundries (GF) 180?
• How far are open source tools from commercial tools?
• Could automated layout of standard cells compete with hand layouts in nanometer processes?
• With Moore’s Law slowing down, do any circuit families deserve a second chance?
• Why would nVidia make a 7.5T standard cell library?

Text of the interview is included below.

We submitted for MPW7! I am particularly excited about this submission because we were able to submit the Zero to ASIC course designs as well as the first Tiny Tapeout design.

MPW7 has by far had the most submissions of the MPW shuttles so far with 72 submitted projects as of 13 September.

Congratulations to everyone on the course submission! We had 9 projects from the course, with 1 demo arbitrary function generator from me, a 32-bit RISC-V based processor by Farhad, an in silicon version of Conway’s Game of Life from Uri and a Spiking Neural Network (SNN) accelerator by Peng Zhou. We also implemented 1kByte of RAM with open-source OpenRAM.

Following my interview with Teo on optimising hardware adders, I thought it would be a great project to tapeout on MPW6.

I wrote about the process on twitter:

I'm working on putting @td_ene 's adder work onto MPW6. Work in progress repo here: https://t.co/OBg8jQG1HJ

It was very easy to generate the adders, but I'm getting stuck on instrumenting them. I need to measure the performance inside the chip to get accurate results. pic.twitter.com/3CJvjmNzGI

We submitted for MPW6!

We had 4 submissions from the course, the shared SRAM infrastructure, and I did some work on instrumenting Teo’s hardware adders.

Congratulations to:

• Zorkan ERKAN
• Emre Hepsag
• Gregory Kielian
• Jason K. Eshraghian

for getting your first ASIC designs on the submission!

We also had some people from the course make personal applications for a whole chip:

• Shumpei Kawasaki - MARMOT SOC
• Maximo - Hardware implementation of the Hack Computer from the Nand to Tetris courses,
• Proppy - HSV Mixer

Here’s the github repo for the group submission and the Efabless project.

Proppy has been doing some great work with preparing the open source ASIC tools to work inside Jupyter notebooks. This means that you can now experiment with simulation and ASIC hardening without needing to download or configure the tools.

I think this is going to be of great importance for academia and education:

• Now when people publish papers they can include a link to a notebook that reproduces the published results.
• For education, it’s going to be so much easier to do a class workshop without having to install tools or maintain VMs.

Proppy demonstrated and explained his work in this interview.

Teodor-Dumitru Ene has been doing some interesting work on optimising hardware adders. Until I spoke with him, I didn’t realise how important this basic digital building block really is. An interesting statistic from his presentation slides:

When a RISC-V processor boots into Linux, 65% to 72% of instructions use addition.

By default, Yosys will synthesise something like this:

reg [31:0] a;
reg [31:0] b;
wire sum = a + b;

Using a ‘middle of the road’ adder, that gives medium PPA (power, performance, area) results. Teo has made a Python library and Yosys plugin that allows us to choose between 4 other types of adder:

We submitted for MPW5!

We had 8 submissions from the course, the shared SRAM infrastructure, and I updated my demo designs.

We also had some people from the course make personal applications for a whole chip:

• Steve & Zhenle - PSRAM (HyperRAM) interface with an ACORN PRNG,
• Q3K - simple, microcontroller-style SoC based around a Lanai core,
• Maximo - Hardware implementation of the Hack Computer from the Nand to Tetris courses,
• Zbigniew - A rendering circuit for three blobs and a playable tetris clone.

And thanks to Paweł for updating the shared SRAM blocks.

Yes! All the designs I submitted to MPW1 are working:

• ✅ 7 segment display
• ✅ TPM2137 CTF
• ✅ WS2812 led driver
• ✅ VGA clock
• ✅ Multiplexor

I put together a video to demonstrate them all:

The 4 other designs that were part of this submission were made by friends who I’ve now sent samples to. It’s looking likely that everyone’s designs will work.