We submitted for MPW4! I was pretty pleased we managed to get so much in with such little time and for a tapeout date of New Year’s Eve. We had 9 submissions from the course, with 1 demo project from me and a new version of Maximo’s hacksoc. Uri submitted 3 designs including some custom standard cells in the shape of skulls! We also implemented the shared SRAM, which means that the group projects have access to a local fast memory (like a blockram on an FPGA).

We submitted for MPW3! The tapeout date was delayed by a couple of weeks due to issues with the toolchain. Update! We received silicon in June 2023 (18 months later!) and I was able to get both my designs partially working. MPW3 We had 7 new submissions from the course, 4 repeats from MPW1 and 2 with fixed clock trees, a new wishbone demo from me and the OpenRAM block.

MPW1 seems an age ago, we submitted in December 2020, but it needed some last minute DRC fixes in February. Silicon was received a few weeks ago, and unfortunately we have some serious issues that will prevent most designs from working. This appears to be due to a bad clock tree in the management section of the chip. Additionally, OpenSTA, the tool meant to verify the clock tree was also misconfigured.

In this interview with Matt Guthaus, we talk about: Recap - what is OpenRAM Why do we need a memory compiler like OpenRAM? 3 phases of OpenRAM development What’s changed since FOSSi dialup MPW2 tapeout of OpenRAM Test modes What was hard about MPW2 DRC issues Status of OpenLANE support for OpenRAM Future plans for OpenRAM Access to resistive RAM, hopefully for MPW4 Resources WOSET link: https://woset-workshop.github.io/ MPW2 application: https://platform.efabless.com/projects/187 FOSSi dialup on OpenRAM: https://www.

Tom Spyrou is a long time EDA developer who has worked at large and small companies. In 1988 Developed QTV at VLSI technology. It was the first STA engine to be trusted to sign off devices for fabrication without timing based simulation. He was the original architect of PrimeTime STA algorithm. Manager of Cadence Common timing Engine and precursor to Open Access Senior technical positions at Synopsys, Cadence, Simplex, AMD, Altera and Intel.

I’m very pleased to get OSHWA certification for my ASIC clock. Who knows, maybe this is a world first! The clock was submitted as part of MPW1. We’re expecting silicon back in August/September, so it was time to get the PCB ready and try to source the other components! I started off by forking Sam Littlewood’s carrier board. This is a 4 layer board, but as I don’t need all the signals I was able to get it down to 2 layers for cheaper fabrication.

One of the popular types of entries to MPW1 & 2 have been FPGAs. I have previously spoken with Arya Reais-Parsi about their FPGA project submitted to MPW1. In MPW2 I noticed there were a couple of applications that seemed fairly advanced - especially FuseRISC: 2 RISCV processors with embedded FPGA fabric between them. Dirk & Nguyen kindly allowed me to interview them about: their FABulous eFPGA framework, support for Yosys & NextPNR, parameterisation of the fabric, blockrams with OpenRAM, their MPW applications and previous tape-outs, and their experience with the open source tools.

After 6 months, 90 participants and 14 designs submitted to MPW2, I’m making the Zero to ASIC course even better! One of the things that’s great about the course is that you can proceed at your own pace. I originally set the course length at 6 weeks, but a lot of people want more time than this. To resolve this I have: removed the expiry date on the discord support, removed the expiry date on office hours.

There continues to be a lot of interest about analogue design with the open source PDK. To cover this interest, I’ve previously interviewed: Diego about his opamp, Lakshmi about her PLL and Thomas about his satellite transceiver. One of the big changes in MPW2 was the provision of more analogue support in the form of Caravan - a new harness. This is exciting because one of the key advantages of an ASIC over an FPGA is the mixed signal capability.