The Design Rule Check is part of the PDK. Both the Magic and OpenLane tools make use of it.
It contains rules that check things like:
- The gate of the MOSFET are the correct dimensions,
- Wires on the metal layers are not too narrow and not too close,
- Check that MOSFET gates are protected if they have long connecting wires - this is called an antenna rule.
There are a few thousand rules in the Skywater130 PDK DRC. As the process/node gets smaller, the number of rules increases.
You can find out more about the DRC checks performed by OpenLANE in Mohamed Shalan’s OpenLane FOSSI dialup presentation
It was a great fun way to introduce people to Verilog and basic digital design in general. You don't have to have done tons of FPGA stuff or be an expert at Verilog at all. If you’re interested in hardware in general I'd say it's accessible.