OpenLane is an Open Source ASIC tool. You can download it from here. The installation instructions are pretty straight forwards and it takes about 15 minutes and 3GB of disk space.

For a lot of great information on how it works and what it does, please watch Mohamed Shalan’s OpenLane FOSSI dialup presentation

Here’s the overview:

We put our HDL in at one end, and out the other comes the GDS2 files that are the standard file format for the foundry.

The most fundamental steps are:

• Synthesis
• Floor planning
• Place and Route
• sign off: Layout vs Schematic, Design Rule Check, Static Timing Analysis

To see more about OpenLane’s output files - check this article

OpenROAD

OpenLane is an open source ASIC flow built using OpenROAD. OpenROAD is a project funded by DARPA to develop open source ASIC tooling.

Here is the OpenROAD documentation and Tutorials and some useful resources.

You can watch some interviews I did with Tom Spyrou, lead dev of OpenROAD here:

Tom also did a presentation for OpenTapeOut.

Course feedback

The zero to asic course is a wonderful course put together by Matt . He and his team have meticulously planned the course with lots of good examples and support to get started with the tools for designing your own chips. Hats off to the team for developing such a course and making it available for the users.

Sudhansu (analog course)