What is a macro in chip design?

A macro is a pre-designed intellectual property block that you can use in your design without designing it yourself. Examples include memories, processor cores, SerDes, and PLLs. Macros may have a fixed function or be parameterised.

Why use a memory macro instead of building memory from flip-flops?

A memory created from flip-flops is much bigger, slower, and more power hungry than an optimised memory macro. Memory macros can use special function cells outside the standard cell library to achieve much better density and performance.

OpenRAM is an open source tool that generates memory macros. It creates a macro you can use in your design without dealing with the internal details, and Skywater 130 support was being added and tested in early tapeouts.

Macro

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November 12, 2020

From http://88physicaldesign.blogspot.com/2015/10/what-is-macro.html:

Macros are intellectual properties that you can use in your design. You do not need to design it. For example, memories, processor core, serdes, PLL etc. Macros might have a fixed function, or being parameterised. Your own design could become a fixed-function macro that some other designer could use, but a parameterised macro includes design elements and code that says how to build a macro to suit a particular set of parameters - for instance the number of words in a memory and how many bits wide it is.

A good example would be memory that’s been created by OpenRAM. Typically for larger memories in a design you want to avoid using lots of flip-flops. A memory created from flip-flops is much bigger than something that has been optimised just for data storage. A memory made with flops would also likely be slower and much more power hungry than a sensibly designed memory macro, which might make use of special function cells that are not part of the standard cell library used by synthesis.

OpenRAM creates a macro that you can then use in your design without having to deal with the details inside.

openram

This talk by Matt Guthaus explains OpenRAM and its current status. Skywater 130 support is being added and is being tested in the first tapeouts.

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The Zero To ASIC course took me on a fantastic journey from drawing and simulating a MOSFET, formal verification leading up to implementing a custom design with an open PDK and completely open source tools. The course is crammed full of interesting material with great pacing and support from Matt, and it's been a fantastic opportunity to meet other folks with shared interests and different backgrounds. The course has left me excited with opportunities for new projects and optimism for some working silicon!

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