A netlist is a machine readable file that contains all the connections between all the components in your design.

They are one of the outputs of a Synthesis tool like Yosys.

These examples are taken from http://bygone.clairexen.net/yosys/screenshots.html

If you have a counter design written in an HDL like Verilog

module counter (clk, rst, en, count);

   input clk, rst, en;
   output reg [3:0] count;
   
   always @(posedge clk)
      if (rst)
         count <= 4'd0;
      else if (en)
         count <= count + 4'd1;

endmodule

The output netlist can be visualised like this:

You can see the blocks are fairly ‘high level’, like multiplexors ($mux), or adders ($add). These types of blocks are not part of the Skywater PDK, so they need to be broken down into more simple blocks.

These blocks are now simple enough that they can be mapped onto the standard cells we have in the PDK. The synthesis process is the first step in the OpenLane tool.

Course feedback

If you've got any interest in how the sausage is made you should get on the course and you should dig in and find out more. I mean this was the work of secret witches and wizards in mysterious cloaks casting strange incantations over a cauldron! This was all secret stuff and I love that this project is trying to do to silicon design what the open source community has been trying to do with software for the last 30 years. This feels like the next logical step and I think we'll look back and say well of course you can make your own chips that's just a thing and it will just be obvious and commonplace and I look forward to that.

Jonathan Pallant (digital course)