A netlist is a machine readable file that contains all the connections between all the components in your design.

They are one of the outputs of a Synthesis tool like Yosys.

These examples are taken from http://bygone.clairexen.net/yosys/screenshots.html

If you have a counter design written in an HDL like Verilog

module counter (clk, rst, en, count);

   input clk, rst, en;
   output reg [3:0] count;
   
   always @(posedge clk)
      if (rst)
         count <= 4'd0;
      else if (en)
         count <= count + 4'd1;

endmodule

The output netlist can be visualised like this:

You can see the blocks are fairly ‘high level’, like multiplexors ($mux), or adders ($add). These types of blocks are not part of the Skywater PDK, so they need to be broken down into more simple blocks.

These blocks are now simple enough that they can be mapped onto the standard cells we have in the PDK. The synthesis process is the first step in the OpenLane tool.

Course feedback

For a very long time I’ve been fascinated by ASICs and have been close to them in my professional life as well, but not really as much into the detail as I would want. It’s been a fascination since grad school at least, so I've been interested in seeing more open source alternatives crop up, and now with the skywater PDK and OpenLane it seemed like the right time. It’s still a bit hard to get the motivation to get started, it feels like a bit of a hurdle so when I saw this course I just jumped right on it. It felt like a perfect way to get started.

Klas Nordmark (digital course)