A netlist is a machine readable file that contains all the connections between all the components in your design.
They are one of the outputs of a Synthesis tool like Yosys.
These examples are taken from http://www.clifford.at/yosys/screenshots.html
If you have a counter design written in an HDL like Verilog
module counter (clk, rst, en, count);
input clk, rst, en;
output reg [3:0] count;
always @(posedge clk)
count <= 4'd0;
else if (en)
count <= count + 4'd1;
The output netlist can be visualised like this:
You can see the blocks are fairly ‘high level’, like multiplexors ($mux), or adders ($add). These types of blocks are not part of
the Skywater PDK, so they need to be broken down into more simple blocks.
These blocks are now simple enough that they can be mapped onto the standard cells we have in the PDK.
The synthesis process is the first step in the OpenLane tool.
It’s a fairly daunting prospect going into something like an ASIC, but I feel confident now that I could pick another project up and go from the start with the Verilog and end up with something that will hopefully work.