A netlist is a machine readable file that contains all the connections between all the components in your design.
They are one of the outputs of a Synthesis tool like Yosys.
These examples are taken from http://bygone.clairexen.net/yosys/screenshots.html
If you have a counter design written in an HDL like Verilog
module counter (clk, rst, en, count);
input clk, rst, en;
output reg [3:0] count;
always @(posedge clk)
count <= 4'd0;
else if (en)
count <= count + 4'd1;
The output netlist can be visualised like this:
You can see the blocks are fairly ‘high level’, like multiplexors ($mux), or adders ($add). These types of blocks are not part of
the Skywater PDK, so they need to be broken down into more simple blocks.
These blocks are now simple enough that they can be mapped onto the standard cells we have in the PDK.
The synthesis process is the first step in the OpenLane tool.
The Zero to ASIC course was great! Through this course I became more proficient with Verilog and started to not just appreciate, but actually enjoy the design verification! It offers the glimpse at the superpower too - seeing the traces of the original design in what used to be just squiggly lines of the masks before. Plus, I am getting my own piece of a silicon 🙂