Sam Zeloof did a great talk about his home IC foundry at the Hackaday Supercon 2019.
This slide shows an overview of the process:
A series of masks is used to build up a 3 dimensional structure on the wafer.
Each step is fundamentally the same:
- coat the wafer in photo resist
- bake it
- use a mask to cover certain areas and use light (often UV) to illuminate the areas not covered
- develop the mask, which will wash out the areas exposed. This leaves holes through to the previous layer.
- now we can apply a process to the exposed areas. This includes things like:
- growing a layer of silicon dioxide
- growing a layer of polysilicon
- metalising the area
- implanting impurities that change the electrochemical properties
Photolithography is the key that allows us to take the patterns we create in a tool like Magic or OpenLane and miniaturise them down to the nanometer scale. It also lets us easily tile the same design over the wafer to make the individual dies
This cross section shows how the layers are used to build up the 3 dimensional structures that make up the IC.
The Zero to ASIC course was great! Through this course I became more proficient with Verilog and started to not just appreciate, but actually enjoy the design verification! It offers the glimpse at the superpower too - seeing the traces of the original design in what used to be just squiggly lines of the masks before. Plus, I am getting my own piece of a silicon 🙂