A shuttle service is the same as a multi project wafer.

On 30th June 2020, Tim Ansell announced the collaboration between Google and Skywater to provide a free shuttle service in his FOSSI dialup talk.

These slides taken from his talk show the overview:

Caravel

Normally in an MPW you would have the whole die to yourself. In the Google/Skywater Shuttle all the designs will be within the user project area of the Caravel harness. Caravel has its own RISCV processor and a neat datasheet. The idea here is to make it easier to bring up and debug your designs at the cost of some area.

Read this post to find out what you could fit in the user space.

The Google shuttle will return chips in type of packaging called Wafer Level Chip Scale Packaging.

Requirements

Efabless have put up a page that has more details on the requirements for entry to the shuttle.

Course feedback

The part I enjoyed the most was going back to the Verilog and seeing test benches pass. In particular the waveform viewer. At the latter parts of course you're simulating the entire Caravel system on chip with a RISCV core. Being able to drill down into everything inside that core, I can log the program counter, I can log all the address and data buses and you can just see in exquisite detail what the system is doing, and it's doing that because I programmed it. Being able to drill down into that detail was really fascinating.

Jonathan Pallant (digital course)