Short articles about my experience with the Google/Efabless/Skywater130 ASIC process, interviews and any other related topics I think are interesting.
Interview With Anton Blanchard - Microwatt: a 64 bit OpenPOWER core, VHDL and OpenLane
I interviewed Anton Blanchard about his MPW1 application - a 64bit OpenPOWER core written in VHDL.
We talked about:
- VHDL vs Verilog
- FPGA vs ASIC
- Problems they faced with such a big design
- SRAM vs DFFRAM
- Software vs Hardware mentality
- Fixing bugs and contributing to OpenLane
You can check out the repository here: https://github.com/antonblanchard/microwatt-caravel
Last minute DRC fixes
The story of the first Open Source ASIC shuttle continues!
A few of the applicants to the first shuttle were recently contacted by efabless - they had discovered some DRC issues that couldn’t be waived by the foundry.
In my recent interview with Tim Edwards, he mentioned that Google are paying for a license of Calibre - another swiss army ASIC tool like Magic. This is to help make sure that the OpenLANE DRC hasn’t missed anything.
Interview with Tim Edwards - what happens between ASIC submission and sending to Skywater?
In this interview I talk with Tim Edwards from eFabless. He is their vice president of analog and platform.
We mostly talked about what needs to happen before they send the final files to Skywater.
A lot of the work is infrastructure:
- fetching files,
- compositing IDs,
- generating fill layers,
- a final DRC run.
Interview with Lakshmi S - PLL design
In this interview I talk with Lakshmi S about their shuttle submission.
As well as convering what a PLL is and its component parts, we also answered some interesting questions from the twitter community:
- how long things take to design, what is fun and what is frustrating,
- how to change the PLL’s response,
- why design a integrated loop filter,
- process corners and ngspice
- post silicon testing.
The repository is here.
Interview With Diego Hernando
In this interview I talk with Diego Hernando about their ASIC submission.
They have been working on some analog blocks; mostly op-amps but also including a PLL from another designer.
We discuss the difference between digital and analog design, the tools, simulation, layout and testing.
Here’s the link to the repository
Image Attribution
Image attributions for images used on this website.
Image from Mohamed Shalan
Image from Caravel Datasheet
Image from RFCafe
Image from Caravel Datasheet
Image from Wikipedia
Image from Components 101
Image from Wikipedia
Image from WhaTech
Image from Technocrazed
Image from Zeptobars
Image from Lattice Semiconductor
Image from Lattice Semiconductor
Image from M. Rovitto
Image from Texplained
My first ASIC - MPW1 submitted
Wow! What a journey. I’m very happy to announce our submission is in and accepted. Now we have a long wait to see if it works! (it does! Jump to the end for an update).
Here’s a picture of the final design. The outer edge and the block at the bottom are all part of Caravel, the standard chip format that everyone on the shuttle has to use. It includes a RISCV processor, RAM, UART, a wishbone bus and more.
Interview with Arya Reais-Parsi - FPGA fabric
In this interview I talk with Arya Reais-Parsi about their shuttle submission. They are working with a group of students to create Open Source FPGA fabric that can be put on an ASIC and configured with yosys/nextpnr.
The repository is here.
Interview With Sylvain 'tnt' Munaut: USB peripherals
In this interview I talk with Sylvain ’tnt’ Munaut about his Google/Skywater ASIC application.
The design is especially interesting to me because of the way it merges the SRAM blocks with the logic. This has been a major challenge in my own design.
Here’s the link to the repository
Interview With Vladimir Milovanović - spectrometer with Chisel
In this interview I talk with Vladimir Milovanović about putting a spectrometer on the Google/Skywater/Efabless ASIC shuttle.
He created the design using Chisel.
The repository is here.