I’ve been wanting to try plotting or printing the GDS files from my first ASIC for a while, and finally I’ve had some time to have a play. I used KLayout because it’s easy to change colours, show and hide layers, and export to a high resolution PNG.

I want to make a poster with 3 pictures inside:

1. The whole chip,
2. Zoomed into the VGA clock macro,
3. Zoomed into the standard cells.

Here’s a photo of the print (I know, how meta) of 1:

When I was first testing my designs inside Caravel, I was quite confused about all the GPIO options.

• Each pin has a range of options that can be configured by firmware running on the RISCV processor.
• Each pin can be driven from the processor or your custom design.
• The outputs have separate output enable lines for bi-directional signalling.

I put together an experiment where I tried the most important options and checked the results in a simulation. You can watch the video here:

I interviewed Anton Blanchard about his MPW1 application - a 64bit OpenPOWER core written in VHDL.

We talked about:

• VHDL vs Verilog
• FPGA vs ASIC
• Problems they faced with such a big design
• SRAM vs DFFRAM
• Software vs Hardware mentality
• Fixing bugs and contributing to OpenLane

You can check out the repository here: https://github.com/antonblanchard/microwatt-caravel

The story of the first Open Source ASIC shuttle continues!

A few of the applicants to the first shuttle were recently contacted by efabless - they had discovered some DRC issues that couldn’t be waived by the foundry.

In my recent interview with Tim Edwards, he mentioned that Google are paying for a license of Calibre - another swiss army ASIC tool like Magic. This is to help make sure that the OpenLANE DRC hasn’t missed anything.

In this interview I talk with Tim Edwards from eFabless. He is their vice president of analog and platform.

We mostly talked about what needs to happen before they send the final files to Skywater.

A lot of the work is infrastructure:

• fetching files,
• compositing IDs,
• generating fill layers,
• a final DRC run.

In this interview I talk with Lakshmi S about their shuttle submission.

As well as convering what a PLL is and its component parts, we also answered some interesting questions from the twitter community:

• how long things take to design, what is fun and what is frustrating,
• how to change the PLL’s response,
• why design a integrated loop filter,
• process corners and ngspice
• post silicon testing.

The repository is here.

In this interview I talk with Diego Hernando about their ASIC submission.

They have been working on some analog blocks; mostly op-amps but also including a PLL from another designer.

We discuss the difference between digital and analog design, the tools, simulation, layout and testing.

Here’s the link to the repository

Image attributions for images used on this website.

Image from Mohamed Shalan

Image from Caravel Datasheet

Image from RFCafe

Image from Caravel Datasheet

Image from Wikipedia

Image from Components 101

Image from Wikipedia

Image from WhaTech

Image from Technocrazed

Image from Zeptobars

Image from Lattice Semiconductor

Image from Lattice Semiconductor

Image from M. Rovitto

Image from Texplained

Wow! What a journey. I’m very happy to announce our submission is in and accepted. Now we have a long wait to see if it works! (it does! Jump to the end for an update).

Here’s a picture of the final design. The outer edge and the block at the bottom are all part of Caravel, the standard chip format that everyone on the shuttle has to use. It includes a RISCV processor, RAM, UART, a wishbone bus and more.