Teodor-Dumitru Ene has been doing some interesting work on optimising hardware adders. Until I spoke with him, I didn’t realise how important this basic digital building block really is. An interesting statistic from his presentation slides:

When a RISC-V processor boots into Linux, 65% to 72% of instructions use addition.

By default, Yosys will synthesise something like this:

reg [31:0] a;
reg [31:0] b;
wire sum = a + b;

Using a ‘middle of the road’ adder, that gives medium PPA (power, performance, area) results. Teo has made a Python library and Yosys plugin that allows us to choose between 4 other types of adder:

We submitted for MPW5!

We had 8 submissions from the course, the shared SRAM infrastructure, and I updated my demo designs.

We also had some people from the course make personal applications for a whole chip:

• Steve & Zhenle - PSRAM (HyperRAM) interface with an ACORN PRNG,
• Q3K - simple, microcontroller-style SoC based around a Lanai core,
• Maximo - Hardware implementation of the Hack Computer from the Nand to Tetris courses,
• Zbigniew - A rendering circuit for three blobs and a playable tetris clone.

And thanks to Paweł for updating the shared SRAM blocks.

Yes! All the designs I submitted to MPW1 are working:

• ✅ 7 segment display
• ✅ TPM2137 CTF
• ✅ WS2812 led driver
• ✅ VGA clock
• ✅ Multiplexor

I put together a video to demonstrate them all:

The 4 other designs that were part of this submission were made by friends who I’ve now sent samples to. It’s looking likely that everyone’s designs will work.

I submitted my first ASIC designs to the free Google shuttle in December of 2020.

In October 2021, we heard there were serious clock related problems with the management area of the chip due to issues with the toolchain. It seemed unlikely that anyone would be able to get anything beyond a single blinking LED from MPW1. The hold violations in the management system meant that the PicoRV32 cpu couldn’t run and setup the GPIOs. So even if our designs work, we can’t get access to them.

I have slowly been learning how to use Github actions to help me build microchips.

It’s harder than it should be to get a working toolchain up. There are lots of repositories, submodules, docker images, environment variables, and they all have to be exactly right. If not, either the flow won’t work correctly, or you’ll make some GDS that will fail the precheck or tapeout tests.

For the course, I have a VM and a set of instructions to do a manual install.

We submitted for MPW4! I was pretty pleased we managed to get so much in with such little time and for a tapeout date of New Year’s Eve.

We had 9 submissions from the course, with 1 demo project from me and a new version of Maximo’s hacksoc. Uri submitted 3 designs including some custom standard cells in the shape of skulls!

We also implemented the shared SRAM, which means that the group projects have access to a local fast memory (like a blockram on an FPGA).

We submitted for MPW3! The tapeout date was delayed by a couple of weeks due to issues with the toolchain.

Update!

We received silicon in June 2023 (18 months later!) and I was able to get both my designs partially working.

MPW3

We had 7 new submissions from the course, 4 repeats from MPW1 and 2 with fixed clock trees, a new wishbone demo from me and the OpenRAM block.

MPW1 seems an age ago, we submitted in December 2020, but it needed some last minute DRC fixes in February.

Silicon was received a few weeks ago, and unfortunately we have some serious issues that will prevent most designs from working. This appears to be due to a bad clock tree in the management section of the chip. Additionally, OpenSTA, the tool meant to verify the clock tree was also misconfigured.

The initial announcement is here.

In this interview with Matt Guthaus, we talk about:

• Recap - what is OpenRAM
• Why do we need a memory compiler like OpenRAM?
• 3 phases of OpenRAM development
• What’s changed since FOSSi dialup
• MPW2 tapeout of OpenRAM
• Test modes
• What was hard about MPW2
• DRC issues
• Status of OpenLANE support for OpenRAM
• Future plans for OpenRAM
• Access to resistive RAM, hopefully for MPW4

Resources

• WOSET link: https://woset-workshop.github.io/
• MPW2 application: https://platform.efabless.com/projects/187
• FOSSi dialup on OpenRAM: https://www.youtube.com/watch?v=9Lw83kFtnc4

Tom Spyrou is a long time EDA developer who has worked at large and small companies.

• In 1988 Developed QTV at VLSI technology. It was the first STA engine to be trusted to sign off devices for fabrication without timing based simulation.
• He was the original architect of PrimeTime STA algorithm.
• Manager of Cadence Common timing Engine and precursor to Open Access
• Senior technical positions at Synopsys, Cadence, Simplex, AMD, Altera and Intel.

Since 2019 he has been the Chief Architect and Technical Project Manager of OpenROAD since 2019.