Want to learn how to design chips?

Learn to design your own ASIC and get it fabricated! Thanks to the new open source Process Development Kit from Google and Skywater and the OpenLane ASIC tools from Efabless, we now have the opportunity to get involved in this exciting field without signing NDAs or paying a fortune for tool licenses.

This article will give you some insight into my journey into the world of analog microelectronics, as told in my recent talk at ORConf 2024.

Back in 2020, inspired by Tim Ansell’s announcement of free tapeouts, I jumped headfirst into the world of open-source ASIC design. My first chip was a digitally focused project, reflecting my background in FPGA programming. It was amazing to see the power of digital abstraction—designing with ones and zeros, instantiating tons of transistors with a single line of code—but it also made me appreciate the incredible complexity hidden beneath the surface.

Hi and happy new year! Welcome to my year in review video of 2023. We’ll revisit the biggest moments of open source semiconductors, the goals I failed and those I met, and set some new ones for 2024!

So, let’s start with the biggest news of 2023.

Last year saw the end of the Google sponsored lottery shuttles. We were expecting around another 8 shuttles for sky130, GF180 and the start of sky90. The last shuttle was GFMPW1, which closed late last year and the Sky 130 PDK is now in the safe hands of the chips alliance.

We submitted Tiny Tapeout 2 back in December, and last week I received the chips from Efabless.

Most first chip designs fail, but you never hear about it because the big companies keep it a secret. So we thought - why not do the world’s first public silicon bring up?

Thankfully the chips worked, and you can watch the whole stream here.

We’ve since found 1 errata, but luckily not a show stopper.

I’m very happy to have over 140 designs from 30 countries submitted to Tiny Tapeout 4!

Top level statistics:

• Total standard cells 82126
• Maximum cells used was 6813 for project 033
• Maximum utilisation was 87.18% for project 016
• Total wire length was 2607 mm

Thanks to everyone who submitted and all the contributors. Also a huge thanks to Efabless Corporation for sponsoring the project!

Tiny Tapeout 5 is already open and will close in early November 2023.

Welcome to my highlights from 2022! It was a big year for open-source silicon, especially the Zero to ASIC course and Tiny Tapeout. Let’s look at some of the highlights and then some aims for 2023.

Here are a few of the highlights:

• Four Zero to ASIC course tapeouts: MPW5, MPW6, MPW7, and MPW8
• Rolled out Tiny Tapeout 1 and 2, helping nearly 250 people tapeout their designs,
• I personally submitted my 19th tapeout
• Presented and hosted a Tiny Tapeout workshop at the Hackaday SuperCon in Novemeber 2022. Met tons of people, including Sam Zeloof @szeloof.
• YouTube Channel had 82k views and 2.5k new subscribers
• Introduced Siliwiz

Zero to ASIC course Tapeouts

The Zero to ASIC course continued to grow, we now have 280 students and made submissions to four multi-project wafers (MPW).

ASIC development tools have often been inaccessible due to cost and complexity. Even as free, open-source tools have become available, the complexity of building and installing the tools has slowed their use by would-be designers.

A challenge in making ASIC development more accessible has been to provide free, easy-to-use development tools. Thankfully development of cloud-based tools using open-source software are making chip design easier than ever.

In June 2022, I had the chance to talk with @Proppy, a Tokyo-based Google engineer who’s enabling people to collaborative ASIC in the cloud with Jupyter and Colab notebooks.

An exciting new opportunity for developing open-source silicon reached fruition at the end of 2022!

GlobalFoundries (GF) teamed up with Google to fund open-source projects using GF’s foundry and their open-source 180nm PDK GF180.

Open-source PDKs like GF180 and Skywater 130nm are essential for making silicon design more accessible. To now have GlobalFoundries involved with fabricating designs will hopefully mean increased opportunities to turn designs into silicon.

GF180’s first multi-project wafer (MPW) tapeout was in December 2022, and several people from the Zero to ASIC and Tiny Tapeout communities were able to submit designs. Here are some highlights:

Using the Tiny User Project tool, people can quickly submit a Tiny Tapeout design to the MPW lottery. The low barrier to entry makes this a great tool to try variations on a design, test faster I/O speeds on an MPW tapeout, or simply compare tapeout processes using a different submission venue.

@Proppy developed the an easy-to-use tool as an extension to the Tiny Tapeout flow.

Proppy’s template repository uses GitHub actions to add a design to the Efabless Caravel User Project. The actions automatically perform the steps requried to harden the design, generate the necessary GDS files, and even generate a convenient GDS viewer. Additionally, the actions output useful reports on cell resource utilization, manufacturability errors, and the precheck results.

I’m happy to announce that Tiny Tapeout 2 was successfully submitted for manufacture in December 2022! 164 designs were included on the tapeout.

Update! Tiny Tapeout 2 chips are back and working!

If you’re unfamiliar, Tiny Tapeout is an educational project that makes it easier and cheaper than ever to get your digital designs manufactured on a real chip! We had a first trial, Tiny Tapeout in September 2022 that was destined for MPW7.

I am excited to introduce a grant for the Zero to ASIC course.

The grant will provide a Silicon-level ticket for selected participants. Two grants will be awarded per month.

Course goals

This course aims to revolutionize open-source silicon by training engineers, hobbyists and enthusiasts to make their own ASICs. During the course, you will design a circuit that will be submitted to the Google lottery MPW to be manufactured in silicon!

We submitted for MPW8! Special congratulations to Adrian Wong for the course submission!

We still managed to get 4 projects in the submission…not bad for a deadline of New Year’s Eve.

The projects include a partial implementation of an L1 GPS tracking channel by Adrian Wong, a Simon Says game implementated by Uri Shaked, and 2 demo submissions (frequency counter and RGB mixer) from me.

Here’s the github repo for the group submission and the Efabless project.

Welcome to the September 2022 monthly update!

Here are the main topics from last month:

• MPW7 submission,
• MPW2 updates,
• Job posting at E-Fabless,
• New videos,
• Is it the end for UVM? and
• Rendering GDS files with Blender or in your browser

MPW7

The deadline for MPW7 was the 14th of September and the Zero to ASIC course submitted another set of projects. Special shout out to Farhad, Peng and James who are all first time tape outs on the project. Well done everyone!

The 3D structures created within a silicon die are spectacular to see.

Thanks to Maximo (@maxiborga on Twitter), there’s now a video for 3D rendering ASIC designs enabling anyone to convert their ASIC design into a beautiful 3D rendering.

3D-rendered chip in Blender

His walkthrough shows how to convert GDS to STL files, enabling you to import the files in image editing software like Blender.

ASICs pack in billions of transistors per square centimeter, making their construction and functionality impossible to understand with the naked eye.

In fact, the upcoming 2 nanometer technology will be so small* that the transistor dimensions will only be 20X larger than an individual atom.

Wouldn’t it be great to see how ASICs are built in 3D at a scale that our bulky human hands can appreciate?

Well wait no longer! Thanks to Thorsten Knoll’s guide, you can now 3D print the cells that make up an ASIC using the GDS files.

We submitted for MPW7! I am particularly excited about this submission because we were able to submit the Zero to ASIC course designs as well as the first Tiny Tapeout design.

MPW7 has by far had the most submissions of the MPW shuttles so far with 72 submitted projects as of 13 September.

Congratulations to everyone on the course submission! We had 9 projects from the course, with 1 demo arbitrary function generator from me, a 32-bit RISC-V based processor by Farhad, an in silicon version of Conway’s Game of Life from Uri and a Spiking Neural Network (SNN) accelerator by Peng Zhou. We also implemented 1kByte of RAM with open-source OpenRAM.

We submitted for MPW6!

We had 4 submissions from the course, the shared SRAM infrastructure, and I did some work on instrumenting Teo’s hardware adders.

Congratulations to:

• Zorkan ERKAN
• Emre Hepsag
• Gregory Kielian
• Jason K. Eshraghian

for getting your first ASIC designs on the submission!

We also had some people from the course make personal applications for a whole chip:

• Shumpei Kawasaki - MARMOT SOC
• Maximo - Hardware implementation of the Hack Computer from the Nand to Tetris courses,
• Proppy - HSV Mixer

Here’s the github repo for the group submission and the Efabless project.

We submitted for MPW5!

We had 8 submissions from the course, the shared SRAM infrastructure, and I updated my demo designs.

We also had some people from the course make personal applications for a whole chip:

• Steve & Zhenle - PSRAM (HyperRAM) interface with an ACORN PRNG,
• Q3K - simple, microcontroller-style SoC based around a Lanai core,
• Maximo - Hardware implementation of the Hack Computer from the Nand to Tetris courses,
• Zbigniew - A rendering circuit for three blobs and a playable tetris clone.

And thanks to Paweł for updating the shared SRAM blocks.

Yes! All the designs I submitted to MPW1 are working:

• ✅ 7 segment display
• ✅ TPM2137 CTF
• ✅ WS2812 led driver
• ✅ VGA clock
• ✅ Multiplexor

I put together a video to demonstrate them all:

The 4 other designs that were part of this submission were made by friends who I’ve now sent samples to. It’s looking likely that everyone’s designs will work.

I submitted my first ASIC designs to the free Google shuttle in December of 2020.

In October 2021, we heard there were serious clock related problems with the management area of the chip due to issues with the toolchain. It seemed unlikely that anyone would be able to get anything beyond a single blinking LED from MPW1. The hold violations in the management system meant that the PicoRV32 cpu couldn’t run and setup the GPIOs. So even if our designs work, we can’t get access to them.

We submitted for MPW4! I was pretty pleased we managed to get so much in with such little time and for a tapeout date of New Year’s Eve.

We had 9 submissions from the course, with 1 demo project from me and a new version of Maximo’s hacksoc. Uri submitted 3 designs including some custom standard cells in the shape of skulls!

We also implemented the shared SRAM, which means that the group projects have access to a local fast memory (like a blockram on an FPGA).

We submitted for MPW3! The tapeout date was delayed by a couple of weeks due to issues with the toolchain.

Update!

We received silicon in June 2023 (18 months later!) and I was able to get both my designs partially working.

MPW3

We had 7 new submissions from the course, 4 repeats from MPW1 and 2 with fixed clock trees, a new wishbone demo from me and the OpenRAM block.

Hi, I’m Matt Venn!

Matthew Venn is a science & technology communicator and electronic engineer. He brings 20 years of engineering experience to create excellent and innovative learning experiences for people all over the world.

I have helped people like you to tape out on all 6 Google/Efabless shuttles. I can teach you how to design chips and how to get them made!

The really exciting part for me is when you see what you've written actually end up as laid out digital logic.

After 6 months, 90 participants and 14 designs submitted to MPW2, I’m making the Zero to ASIC course even better!

One of the things that’s great about the course is that you can proceed at your own pace. I originally set the course length at 6 weeks, but a lot of people want more time than this. To resolve this I have:

• removed the expiry date on the discord support,
• removed the expiry date on office hours.

To help grow the community and provide another venue for discussing the course, I have added a weekly group call for anyone on the course to join. It’s been going really well; we answer questions, discuss the course and chat about what’s going on in the world of open source ASICs.

Part 1: Schematic Capture with Xschem

While it’s possible to just draw transistors directly - for example in SiliWiz, this doesn’t scale well and gets confusing fast. We want to draw a circuit diagram first, with levels of hierarchy for more complex designs. These can then be simulated and checked that specifications are met before moving onto layout.

Lab 1.1: Try the Xschem demos

• Build Xschem familiarity.
• Experiment with some of the demos that come with the PDK.

Lab 1.2: Draw your own circuit

• Draw your own circuit and get it ready for simulation
• If you don’t have a circuit ready, you can use one of the demos
• Follow best practices

Part 2: Simulation

After you have a schematic and have exported the netlist to a spice file, we can use ngspice to simulate it. In this part of the course you will start to learn spice, using it to simulate demo designs and then your own.

Part 1: MOSFETs and the Skywater130 standard cells

MOSFETs are the building blocks of the chips we will be learning how to make. While we don’t need an in depth knowledge of how they work, it’s useful to see how they are joined together into functional blocks known as standard cells - for example AND gates or Flip-Flops.

• Basic understanding of how MOSFETs work.
• How are they constructed on a silicon wafer.
• How to run a simulation with ngspice.

Project 1.1: Choose a standard cell and simulate it

• Get an overview of what the standard cells are.
• Choose your favourite cell, simulate it and show it does what it should.
• Measure how fast it can propagate signals from input to output.

Project 1.2: Draw a mosfet in magic

• Learn the basics of the Magic VLSI tool.
• Extract the circuit from a drawing.
• Simulate with ngspice.

Part 2: Building Digital Designs

As we are focussing on digital design for making our ASIC we need to be able to efficiently describe the kind of hardware we want. Verilog is one of a few languages used for this purpose. It’s well supported by the Open Source tools.

We did it! 14 people from the course got their designs into the group submission, and the project was accepted for fabrication. Silicon here we come!

You can get all the details on all the projects submitted to MPW2 here - you’ll need to select the MPW2 filter.

And see how I put the application together here, with the repo here.

Project listing

RGB Mixer

• Author: Matt Venn
• Github: https://github.com/mattvenn/wrapped_rgb_mixer/tree/caravel-mpw-two-c
• Description: reads 3 encoders and generates PWM signals to drive an RGB LED

Frequency counter

• Author: Matt Venn
• Github: https://github.com/mattvenn/wrapped_frequency_counter/tree/caravel-mpw-two-c
• Description: Counts pulses on input and displays frequency on 2 seven segment displays

A5/1 Wishbone

• Author: Jamie Iles
• Github: https://github.com/jamieiles/a5-1-wb-macro
• Description: A5/1 cryto block connected via wishbone to PicoRV32

Fibonacci

• Author: Konrad Rzeszutek Wilk
• Github: https://github.com/konradwilk/fibonacci
• Description: Fibonacci emitter connected to [37:8] and controlled via wishbone

Quad PWM FET Drivers

• Author: Chris DePalm
• Github: https://github.com/ChrisDePalm/wrapped_quad_pwm_fet_drivers.git
• Description: 4 PWM FET Drivers for Power Applications

memLCDdriver

• Author: Matt Beach
• Github: https://github.com/matt-beach/wrapped_memLCDdriver.git
• Description: SPI to 64-color memory LCD interface

QARMA-64 Accelerator

• Author: Viktor H. Brange
• Github: https://github.com/vbrange/verilog_qarma
• Description: Implementation of QARMA 64

ChaCha20 Accelerator

• Author: Richard Petri
• Github: https://github.com/rpls/wrapped_chacha_wb_accel
• Description: A minimal Wishbone connected ChaCha20 accelerator

Framebufferless Video Core

• Author: Tom Gwozdz
• Github: https://github.com/tomgwozdz/fbless-graphics-core
• Description: A framebufferless VGA video generator, under CPU control

Pong

• Author: Erik van Zijst
• Github: https://github.com/erikvanzijst/wrapped_pong.git
• Description: A hardware implementation of Pong

Hack soc

• Author: Maximo Balestrini
• Github: https://github.com/mbalestrini/wrapped_hack_soc
• Description: Hardware implementation of the Hack Computer from the Nand to Tetris courses

gfxdemo

• Author: Konrad Beckmann
• Github: https://github.com/kbeckmann/wrapped_gfxdemo
• Description: gfxdemo

Wishbone HyperRAM

• Author: Pawel Sitarz
• Github: https://github.com/embelon/wrapped_wb_hyperram
• Description: Simple HyperRAM driver accesible on Wishbone bus

Newmot SoC

• Author: Charles-Henri Mousset
• Github: https://github.com/chmousset/caravel_multi_newmot
• Description: Simple SoC dmonstrating a Stepper Motor step/dir generator, and litex wishbone / uart / pwm

hoggephase

• Author: David Hulton
• Github: https://github.com/h1kari/wrapped_hoggephase_project
• Description: Hogge Phase EMFI/BBI Glitch Detector

bfloat16_fma

• Author: Author
• Github: https://github.com/etalian/mensa
• Description: dual bfloat16 fused multiply-add

Multi project tools

This time around submission was a lot easier and nerve-wracking than MPW1.

Almost exactly a year ago in March 2020 I started getting interested in Open Source ASIC tooling. I don’t remember exactly what sparked my interest, but I remember this talk by Tim Edwards at WOSH: Bootstrapping a real working design flow and sometime after seeing Adam Zeloof posting a picture of an ASIC implementation of pong.

I began by investigating QFlow. The standard cells used by QFlow were from Oklahoma State University (OSU).

By May I was getting a few results out of QFlow and I was curious to discover how digital logic actually works on silicon. I experimented with Magic and managed to draw and simulate an inverter after taking one of Kunal Ghosh’s VLSI courses.

Wow! What a journey. I’m very happy to announce our submission is in and accepted. Now we have a long wait to see if it works! (it does! Jump to the end for an update).

Here’s a picture of the final design. The outer edge and the block at the bottom are all part of Caravel, the standard chip format that everyone on the shuttle has to use. It includes a RISCV processor, RAM, UART, a wishbone bus and more.

Sign up to the Zero to ASIC course newsletter!

• Discount codes for the course
• Course updates
• Related projects like TinyTapeout and SiliWiz
• Early access to new material
• Interviews & Videos
• News from the world of open source silicon

What I learned in 6 weeks in this course would have taken me 6 months on my own. This is a great way to accelerate it.

Awesome opensource ASIC resources

• Awesome opensource ASIC resources

Talks, Interviews & Podcast

• Zero to ASIC Hackaday #remoticon talk on youtube and slides
• Zero to ASIC emBO++ talk and slides
• Discussion with Robert Feranec
• Zero to ASIC course interviews
• Zero to ASIC course podcast

FOSSi Dialup

• FOSSi foundation dialup talks

SkyWater/Google discussion & announcements

• Google/SkyWater Slack
• PDK docs
• Announce mailing list

Tools

• OpenLane & Documentation
• OpenLane summary tool helps to explore the OpenLane output files.
• Magic
• KLayout
• Open Source FPGA toolchain

Courses

• My digital course
• My analog course
• Kunal’s udemy courses
• Nand 2 Tetris

Books

• CMOS VLSI Design by Weste & Harris: Expensive but excellent.
• Introduction to VLSI systems by Carver Mead & Lynn Conway: Old but good.

FPGA

• FPGA boards: iCEBreaker, TinyFPGA, Black Ice
• Will Green’s Project F
• WTFPGA course

Want to learn how to design analog and mixed signal chips?

The Zero to ASIC Analog course will guide you through the process of taping out analog integrated circuits using open-source tools. While digital design often relies on hardware description languages and automated synthesis, analog design involves more in depth simulation and drawing circuit layouts by hand. You’ll learn to use tools like Xschem for schematic capture, NGspice for simulation, and Magic for layout.