We submitted for MPW6!
We had 4 submissions from the course, the shared SRAM infrastructure, and I did some work on instrumenting Teo’s hardware adders.
- Zorkan ERKAN
- Emre Hepsag
- Gregory Kielian
- Jason K. Eshraghian
for getting your first ASIC designs on the submission!
We also had some people from the course make personal applications for a whole chip:
Here’s the github repo for the group submission and the Efabless project.
Building and testing the application
To see how I put the application together check the multi_project_tools.
I finally got github actions working on both the main repository and the individual submission template.
The main repo action checks the following:
- all tests pass for all the projects
- caravel tests pass
- formal proof of the tristate bus - thanks to YosysHQ formal verification tools
- builds the GDS and runs the precheck
The submission template github action checks all the tests are passing for that project. Tests include:
- functional RTL test
- caravel test pass
- project has tristate buffers and they work
- ports are correct for integration into the group submission
- GDS nothing above metal 5
- LVS matches gatelevel verilog to GDS
- documentation is present
And here’s a list of the projects - congratulations everyone!
instrumented adder - behavioural
instrumented adder - sklansky
instrumented adder - Brent Kung
instrumented adder - Ripple carry
instrumented adder - Kogge Stone