We submitted for MPW3! The tapeout date was delayed by a couple of weeks due to issues with the toolchain.
We received silicon in June 2023 (18 months later!) and I was able to get both my designs partially working.
We had 7 new submissions from the course, 4 repeats from MPW1 and 2 with fixed clock trees, a new wishbone demo from me and the OpenRAM block.
We also had some people course make personal applications for a whole chip:
The github repo for the group submission is here: https://github.com/mattvenn/zero_to_asic_mpw3
And the Efabless project is here: https://platform.efabless.com/projects/392
To see how I put the application together check here.
- Author: Ameet Gohil
- Github: https://github.com/ameetgohil/mpw3-nco
- commit: 6050985fcc44fba61af68cbc01c7a8e40f0a61dc
- Description: generates signed sin and cos outputs given an angle accessible via wishbone
The multi project tools have continued to improve:
- Added some new tests
- Optional ports, which means you can turn off the ones you don’t want, allowing smaller macros
- Support for different size macros
- Added OpenRAM instance for fast local memory
- Auto generate the cover image
- Support for MPW3 OpenLane tooling
- Can fetch all the project’s repos
This is what I do to build the project:
./multi_tool.py --config projects.yaml --force-delete --clone --copy-gds --generate-doc --annotate --create-openlane-config --openram
- clones all the repos
- copies the GDS, LEF and Verilog to the right place
- generates doc and annotated image
- generates the macro positiioning and OpenLane config
- includes OpenRAM support
I’d like to say thanks to Paweł for all his work on integrating OpenRAM. It was much harder than it should have been and it wouldn’t have got done without him.
I’ll be making an OpenRAM tutorial soon to help document how to use it.