My first ASIC - MPW1 submitted

Wow! What a journey. I’m very happy to announce our submission is in and accepted. Now we have a long wait to see if it works! (it does! Jump to the end for an update).

Here’s a picture of the final design. The outer edge and the block at the bottom are all part of Caravel, the standard chip format that everyone on the shuttle has to use. It includes a RISCV processor, RAM, UART, a wishbone bus and more.

The cross hatching between all the project macros (yellow blocks) is the power distribution network. It’s a fine grid of the 4 power supplies. As they pass over macro, a via connects the power lines of the macro to the power distribution network.

ASIC

1 seven-segment-seconds

2 mm2hdmi

3 asicfreq

4 TPM2137

5 ws2812

6 spinet

7 ASIC_watch

8 vga-clock

9 multi project harness

OpenLane configuration

The configuration for each of the above project macros is here.

For the details on joining them all together and placing on the Caravel harness, you can check the application repository here. The configuration is on a different branch here.

It all got a bit messy at the end because there was a last minute change of the Caravel harness. This meant that I had to use one branch (release) for building the user project area, and then another branch (release-mpw-one-b) for building the final GDS files for submission.

Stuff that didn’t get done

Unfortunately I didn’t manage to get any artwork placed. There wasn’t a good way to integrate it with the tools, so it would have meant manually altering the power distribution network to remove wires, and then manually place the artwork blocks. I just didn’t feel confident enough to do it without wrecking something - and I was really tired! So hopefully next time I will have worked it out.

Update