HDL
A Hardware Description Language is used to… describe hardware! So instead of drawing out an inverter using a tool like Magic we can write a line like this:
output = !input;
Which describes what an inverter does. The ! means invert. This is a description of what the circuit does, similar to a programming language like C (although everything happens at once, not in sequence). This is referred to as a ‘register transfer language’ or RTL. You can also describe a circuit schematic in an HDL, and then it is referred to as a netlist.
Common HDLs are Verilog and VHDL. There are also higher level languages like Amaranth, Chisel & Spinal.
The VexRiscv RISCV processor in the harness we use for Efabless submissions is written in Spinal, by Charles Papon.
These are often implemented as a library to a programming language like Python or Scala. Then you can express more complex hardware in fewer lines.
Verilog is the most common HDL and the one most well supported by the Open Source tools. It’s well known for the number of ‘foot guns’ it has! Be careful, describing hardware with an HDL is nothing like programming a CPU with a sequential language like C or Python.
Circuits operate all at once, parallelism is easy. If you want sequences of things you have to build a sequencer first (like a state machine).
A CPU executes one instruction at a time and if you want parallelism you either ‘fake’ it by interleaving programs or you have multiple cores on your CPU.
A good short course (targetted at FPGAs) introducing Verilog is WTFPGA.
A good FPGA resource is Will’s Project F.
After writing your design in an HDL, you have to synthesise into a netlist so it can be recreated in the actual building blocks you have in the PDK
Course feedback
I would recommend this course to people who don't have any awareness of open source hardware development. It can be a bit of an eye opener, a lot of people in industry have a disconnected impression of what the landscape really is.