I’m happy to announce that Tiny Tapeout 2 was successfully submitted for manufacture in December 2022! 164 designs were included on the tapeout.

Update! Tiny Tapeout 2 chips are back and working!

If you’re unfamiliar, Tiny Tapeout is an educational project that makes it easier and cheaper than ever to get your digital designs manufactured on a real chip! We had a first trial, Tiny Tapeout in September 2022 that was destined for MPW7.

I am excited to introduce a grant for the Zero to ASIC digital course.

The grant will provide a Silicon-level ticket for selected participants. Two grants will be awarded per month.

The grant is for people who are unable to pay the full price, please only apply if you need it.

Course goals

This course aims to revolutionize open-source silicon by training engineers, hobbyists and enthusiasts to make their own ASICs. During the course, you will design a circuit that will be submitted to Tiny Tapeout to be manufactured in silicon!

We submitted for MPW8! Special congratulations to Adrian Wong for the course submission!

We still managed to get 4 projects in the submission…not bad for a deadline of New Year’s Eve.

The projects include a partial implementation of an L1 GPS tracking channel by Adrian Wong, a Simon Says game implementated by Uri Shaked, and 2 demo submissions (frequency counter and RGB mixer) from me.

Here’s the github repo for the group submission and the Efabless project.

SiliWiz will help you get a basic understanding of how semiconductors work and are manufactured at a fundamental level. It’s a free and open source tool that you can play with in your browser.

Aims

• Draw your own logic gate and understand how that gate would be manufactured in a foundry.
• Learn how the gate is built out of the fundamental circuit elements used in chip design
• Understand how the drawings are used to manufacture the chip
• Be aware of some of SiliWiz’s limitations and simplifications

Lessons

We have a set of free lessons that guide you through from drawing and simulating resistors all the way up to a CMOS inverter.

Welcome to the September 2022 monthly update!

Here are the main topics from last month:

• MPW7 submission,
• MPW2 updates,
• Job posting at E-Fabless,
• New videos,
• Is it the end for UVM? and
• Rendering GDS files with Blender or in your browser

MPW7

The deadline for MPW7 was the 14th of September and the Zero to ASIC course submitted another set of projects. Special shout out to Farhad, Peng and James who are all first time tape outs on the project. Well done everyone!

The 3D structures created within a silicon die are spectacular to see.

Thanks to Maximo (@maxiborga on Twitter), there’s now a video for 3D rendering ASIC designs enabling anyone to convert their ASIC design into a beautiful 3D rendering.

3D-rendered chip in Blender

His walkthrough shows how to convert GDS to STL files, enabling you to import the files in image editing software like Blender.

ASICs pack in billions of transistors per square centimeter, making their construction and functionality impossible to understand with the naked eye.

In fact, the upcoming 2 nanometer technology will be so small* that the transistor dimensions will only be 20X larger than an individual atom.

Wouldn’t it be great to see how ASICs are built in 3D at a scale that our bulky human hands can appreciate?

Well wait no longer! Thanks to Thorsten Knoll’s guide, you can now 3D print the cells that make up an ASIC using the GDS files.

In this interview with Professor James Stine, we talk about:

• Why is Open Source the key to innovation?
• What do students struggle with most when learning to design standard cell libraries?
• What are the biggest misconceptions engineers have about standard cells?
• What’s James’ tool flow?
• How many cells are needed to make a library?
• Why do we need another library for Global Foundries (GF) 180?
• How far are open source tools from commercial tools?
• Could automated layout of standard cells compete with hand layouts in nanometer processes?
• With Moore’s Law slowing down, do any circuit families deserve a second chance?
• Why would nVidia make a 7.5T standard cell library?

Text of the interview is included below.

We submitted for MPW7! I am particularly excited about this submission because we were able to submit the Zero to ASIC course designs as well as the first Tiny Tapeout design.

MPW7 has by far had the most submissions of the MPW shuttles so far with 72 submitted projects as of 13 September.

Congratulations to everyone on the course submission! We had 9 projects from the course, with 1 demo arbitrary function generator from me, a 32-bit RISC-V based processor by Farhad, an in silicon version of Conway’s Game of Life from Uri and a Spiking Neural Network (SNN) accelerator by Peng Zhou. We also implemented 1kByte of RAM with open-source OpenRAM.

Following my interview with Teo on optimising hardware adders, I thought it would be a great project to tapeout on MPW6.

I wrote about the process on twitter:

I'm working on putting @td_ene 's adder work onto MPW6. Work in progress repo here: https://t.co/OBg8jQG1HJ

It was very easy to generate the adders, but I'm getting stuck on instrumenting them. I need to measure the performance inside the chip to get accurate results. pic.twitter.com/3CJvjmNzGI