Short articles about my experience with making ASICs, interviews and any other related topics I think are interesting.

Interview With Matt Guthaus


In this interview with Matt Guthaus, we talk about:

  • Recap - what is OpenRAM
  • Why do we need a memory compiler like OpenRAM?
  • 3 phases of OpenRAM development
  • What’s changed since FOSSi dialup
  • MPW2 tapeout of OpenRAM
  • Test modes
  • What was hard about MPW2
  • DRC issues
  • Status of OpenLANE support for OpenRAM
  • Future plans for OpenRAM
  • Access to resistive RAM, hopefully for MPW4

Resources

Interview With Tom Spyrou


Tom Spyrou is a long time EDA developer who has worked at large and small companies.

  • In 1988 Developed QTV at VLSI technology. It was the first STA engine to be trusted to sign off devices for fabrication without timing based simulation.
  • He was the original architect of PrimeTime STA algorithm.
  • Manager of Cadence Common timing Engine and precursor to Open Access
  • Senior technical positions at Synopsys, Cadence, Simplex, AMD, Altera and Intel.

Since 2019 he has been the Chief Architect and Technical Project Manager of OpenROAD since 2019.

World's first certified open source hardware down to the chip level?


I’m very pleased to get OSHWA certification for my ASIC clock. I’m pretty sure this is the world’s first certified open source hardware down to the chip level!

Update! The PCB has been updated here.

The clock was submitted as part of MPW1. We’re expecting silicon back in August/September, so it was time to get the PCB ready and try to source the other components!

I started off by forking Sam Littlewood’s carrier board. This is a 4 layer board, but as I don’t need all the signals I was able to get it down to 2 layers for cheaper fabrication. OSHPark have sponsored the board in their special ‘after dark’ finish.

Interview With Dirk Koch and Nguyen Dao


One of the popular types of entries to MPW1 & 2 have been FPGAs. I have previously spoken with Arya Reais-Parsi about their FPGA project submitted to MPW1.

In MPW2 I noticed there were a couple of applications that seemed fairly advanced - especially FuseRISC: 2 RISCV processors with embedded FPGA fabric between them.

fuserisc

Dirk & Nguyen kindly allowed me to interview them about:

  • their FABulous eFPGA framework,
  • support for Yosys & NextPNR,
  • parameterisation of the fabric,
  • blockrams with OpenRAM,
  • their MPW applications and previous tape-outs, and
  • their experience with the open source tools.

Enjoy!

Course Improvements


After 6 months, 90 participants and 14 designs submitted to MPW2, I’m making the Zero to ASIC course even better!

One of the things that’s great about the course is that you can proceed at your own pace. I originally set the course length at 6 weeks, but a lot of people want more time than this. To resolve this I have:

  • removed the expiry date on the discord support,
  • removed the expiry date on office hours.

To help grow the community and provide another venue for discussing the course, I have added a weekly group call for anyone on the course to join. It’s been going really well; we answer questions, discuss the course and chat about what’s going on in the world of open source ASICs.

Livestream with Thomas Parry: analogue design with the open source ASIC tools


There continues to be a lot of interest about analogue design with the open source PDK.

To cover this interest, I’ve previously interviewed:

One of the big changes in MPW2 was the provision of more analogue support in the form of Caravan - a new harness. This is exciting because one of the key advantages of an ASIC over an FPGA is the mixed signal capability.

MPW2 Submitted


We did it! 14 people from the course got their designs into the group submission, and the project was accepted for fabrication. Silicon here we come!

MPW2 submission

You can get all the details on all the projects submitted to MPW2 here - you’ll need to select the MPW2 filter.

And see how I put the application together here, with the repo here.

Project listing

RGB Mixer

Frequency counter

A5/1 Wishbone

Fibonacci

Quad PWM FET Drivers

memLCDdriver

QARMA-64 Accelerator

ChaCha20 Accelerator

Framebufferless Video Core

Pong

Hack soc

gfxdemo

Wishbone HyperRAM

Newmot SoC

hoggephase

bfloat16_fma

Multi project tools

This time around submission was a lot easier and nerve-wracking than MPW1.

Caravel Wishbone Demo


Caravel is the name of the harness provided by Efabless to make it easier to submit a design to the foundry.

Among other things, it provides:

  • The padring
  • 3kB of memory
  • A small RISCV processor called PicoRV32
  • GPIOs
  • A logic analyser
  • A Wishbone bus

For the full details, check the documentation

The simplest way to interface between your project and the PicoRV32 is probably the logic analyser. This gives you 128 ins and outs that you can use to configure or debug your design.

MPW2 announced by Efabless


Efabless have announced MPW2! The closing date is the 18th of June.

The biggest changes are:

  • OpenLANE ASIC flow updated to rc0.15
  • Caravel has become caravel_user_project at the mpw-two-c tag:
    • smaller repo size includes a ‘Caravel Lite’ submodule
    • new IRQ ports
    • logic analyser registers renamed
  • An alternative analogue specific ‘Caravan’ harness
  • The submission process has been streamlined to make it faster and easier to submit

You can browse the current applications here: https://platform.efabless.com/projects/shuttle_name/MPW-2

Interview With Dan Rodrigues - first shuttle, racing the beam & retro gaming


In this interview Dan and I talk about his submission to the first shuttle, simulating video projects, how to do graphics with no frame buffer and the joys of retro gaming.