After 6 months, 90 participants and 14 designs submitted to MPW2, I’m making the Zero to ASIC course even better!

One of the things that’s great about the course is that you can proceed at your own pace. I originally set the course length at 6 weeks, but a lot of people want more time than this. To resolve this I have:

• removed the expiry date on the discord support,
• removed the expiry date on office hours.

To help grow the community and provide another venue for discussing the course, I have added a weekly group call for anyone on the course to join. It’s been going really well; we answer questions, discuss the course and chat about what’s going on in the world of open source ASICs.

There continues to be a lot of interest about analogue design with the open source PDK.

To cover this interest, I’ve previously interviewed:

• Diego about his opamp,
• Lakshmi about her PLL and
• Thomas about his satellite transceiver.

One of the big changes in MPW2 was the provision of more analogue support in the form of Caravan - a new harness. This is exciting because one of the key advantages of an ASIC over an FPGA is the mixed signal capability.

We did it! 14 people from the course got their designs into the group submission, and the project was accepted for fabrication. Silicon here we come!

You can get all the details on all the projects submitted to MPW2 here - you’ll need to select the MPW2 filter.

And see how I put the application together here, with the repo here.

Project listing

RGB Mixer

• Author: Matt Venn
• Github: https://github.com/mattvenn/wrapped_rgb_mixer/tree/caravel-mpw-two-c
• Description: reads 3 encoders and generates PWM signals to drive an RGB LED

Frequency counter

• Author: Matt Venn
• Github: https://github.com/mattvenn/wrapped_frequency_counter/tree/caravel-mpw-two-c
• Description: Counts pulses on input and displays frequency on 2 seven segment displays

A5/1 Wishbone

• Author: Jamie Iles
• Github: https://github.com/jamieiles/a5-1-wb-macro
• Description: A5/1 cryto block connected via wishbone to PicoRV32

Fibonacci

• Author: Konrad Rzeszutek Wilk
• Github: https://github.com/konradwilk/fibonacci
• Description: Fibonacci emitter connected to [37:8] and controlled via wishbone

Quad PWM FET Drivers

• Author: Chris DePalm
• Github: https://github.com/ChrisDePalm/wrapped_quad_pwm_fet_drivers.git
• Description: 4 PWM FET Drivers for Power Applications

memLCDdriver

• Author: Matt Beach
• Github: https://github.com/matt-beach/wrapped_memLCDdriver.git
• Description: SPI to 64-color memory LCD interface

QARMA-64 Accelerator

• Author: Viktor H. Brange
• Github: https://github.com/vbrange/verilog_qarma
• Description: Implementation of QARMA 64

ChaCha20 Accelerator

• Author: Richard Petri
• Github: https://github.com/rpls/wrapped_chacha_wb_accel
• Description: A minimal Wishbone connected ChaCha20 accelerator

Framebufferless Video Core

• Author: Tom Gwozdz
• Github: https://github.com/tomgwozdz/fbless-graphics-core
• Description: A framebufferless VGA video generator, under CPU control

Pong

• Author: Erik van Zijst
• Github: https://github.com/erikvanzijst/wrapped_pong.git
• Description: A hardware implementation of Pong

Hack soc

• Author: Maximo Balestrini
• Github: https://github.com/mbalestrini/wrapped_hack_soc
• Description: Hardware implementation of the Hack Computer from the Nand to Tetris courses

gfxdemo

• Author: Konrad Beckmann
• Github: https://github.com/kbeckmann/wrapped_gfxdemo
• Description: gfxdemo

Wishbone HyperRAM

• Author: Pawel Sitarz
• Github: https://github.com/embelon/wrapped_wb_hyperram
• Description: Simple HyperRAM driver accesible on Wishbone bus

Newmot SoC

• Author: Charles-Henri Mousset
• Github: https://github.com/chmousset/caravel_multi_newmot
• Description: Simple SoC dmonstrating a Stepper Motor step/dir generator, and litex wishbone / uart / pwm

hoggephase

• Author: David Hulton
• Github: https://github.com/h1kari/wrapped_hoggephase_project
• Description: Hogge Phase EMFI/BBI Glitch Detector

bfloat16_fma

• Author: Author
• Github: https://github.com/etalian/mensa
• Description: dual bfloat16 fused multiply-add

Multi project tools

This time around submission was a lot easier and nerve-wracking than MPW1.

Caravel is the name of the harness provided by Efabless to make it easier to submit a design to the foundry.

Among other things, it provides:

• The padring
• 3kB of memory
• A small RISCV processor called PicoRV32
• GPIOs
• A logic analyser
• A Wishbone bus

For the full details, check the documentation

The simplest way to interface between your project and the PicoRV32 is probably the logic analyser. This gives you 128 ins and outs that you can use to configure or debug your design.

Efabless have announced MPW2! The closing date is the 18th of June.

The biggest changes are:

• OpenLANE ASIC flow updated to rc0.15
• Caravel has become caravel_user_project at the mpw-two-c tag:
  • smaller repo size includes a ‘Caravel Lite’ submodule
  • new IRQ ports
  • logic analyser registers renamed
• An alternative analogue specific ‘Caravan’ harness
• The submission process has been streamlined to make it faster and easier to submit

You can browse the current applications here: https://platform.efabless.com/projects/shuttle_name/MPW-2

In this interview Dan and I talk about his submission to the first shuttle, simulating video projects, how to do graphics with no frame buffer and the joys of retro gaming.

• Caravel repo: https://github.com/dan-rodrigues/caravel_vdp_lite
• IceStation32: https://github.com/dan-rodrigues/icestation-32

OpenLANE makes a lot of output files! This can be quite confusing when you’re getting started.

Here’s a useful spreadsheet I made to show:

• the path of the files
• most important files and what they mean
• which tool creates which file

Thanks Amr and Ahmed for helping me with this!

The spreadsheet was updated for MPW2, and there haven’t been major changes in MPW3.

OpenLANE summary tool

I’ve also made a summary tool: https://github.com/mattvenn/openlane_summary

In this interview Thomas talks us through his Amateur satellite transceiver shuttle submission. We also discuss the differences between the Open Source tools and the industry standard ones he uses in his day job.

• Design repo: https://github.com/yrrapt/amsat_txrx_ic
• Caravel repo: https://github.com/yrrapt/caravel_amsat_txrx_ic
• Connect with Thomas on linkedin: https://www.linkedin.com/in/thomas-parry-60419468/

Almost exactly a year ago in March 2020 I started getting interested in Open Source ASIC tooling. I don’t remember exactly what sparked my interest, but I remember this talk by Tim Edwards at WOSH: Bootstrapping a real working design flow and sometime after seeing Adam Zeloof posting a picture of an ASIC implementation of pong.

I began by investigating QFlow. The standard cells used by QFlow were from Oklahoma State University (OSU).

By May I was getting a few results out of QFlow and I was curious to discover how digital logic actually works on silicon. I experimented with Magic and managed to draw and simulate an inverter after taking one of Kunal Ghosh’s VLSI courses.